A modern integrated circuit (IC), for example a flash memory device, may have millions to hundreds of millions of devices made up of complex, multi-layered structures that are fabricated through hundreds of processing steps. Those structures, for example a gate stack, are formed by repeated deposition and patterning of thin films on a silicon substrate, also known as a wafer.
As channel length grows shorter, threshold voltage, the voltage required to turn on a transistor, begins to decrease and leakage current increases. These effects are commonly referred to in the semiconductor arts as the “short channel effects” (SCE). An increase in leakage current is particularly onerous in flash memory devices as flash has found wide acceptance in very low power applications, for example mobile phones, due to the ability of flash to retain information without applied power. Increases in leakage current may have a significant deleterious effect on total power consumption of the flash device and the product using the flash device.
The distance between source and drain regions is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the source and drains, distance between the source and drains regions becomes less than the physical channel length and is often referred to as the effective channel length (Leff). In VLSI designs, as the physical channel becomes small, so must the Leff. SCE becomes a predominant problem whenever Leff drops.
Generally speaking, SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing sub-threshold currents. As Leff becomes quite small, the depletion regions associated with the source and drain areas may extend toward one another and substantially occupy the channel area. Hence, some of the channel will be partially depleted without any influence of gate voltage. As a result, less gale charge is required to invert the channel of a transistor having a short Leff. Somewhat related to threshold voltage lowering is the concept of subthreshold current flow. Even at times when the gate voltage is below the threshold amount, current between the source and drain nonetheless exist for transistors having a relatively short Leff.
Two primary causes of increased sub-threshold current are punch through and drain-induced barrier lowering (DIBL). Punch through results from widening of the drain depletion region when a reverse-bias voltage is applied across the drain-well diode. The electric field of the drain may eventually penetrate to the source area, thereby reducing the potential energy barrier of the source-to-body junction. Punch through current is therefore associated within the substrate bulk material, well below the substrate surface. Contrary to punch through current, DIBL induced current occurs mostly at the substrate surface. Application of a drain voltage can cause the surface potential to be lowered, resulting in a lowered potential energy barrier at the surface, and causing the sub-threshold current in the channel near the silicon—silicon dioxide interface to be increased.
One solution to decrease DIBL has been source side boron implants (SSBI). By using an SSBI, a graded concentration of boron can be driven into the channel region to help reduce DIBL and therefore control short channel effect. However, as the size of the device is reduced, SSBI no longer work as efficiently. For example, short channel effect occurs when the SSBI diffuses into the channel uniformly.
Thus, a need exists for a method and system for improving short channel effect on a floating gate device. A further need exists for a method and system for improving short channel effect on a floating gate device that works with reduced memory device sizes. Yet another need exists for a method and system for improving short channel effect on a floating gate device which meets the above needs and which is compatible with existing memory manufacturing processes.